CRL Hardware team is involved in evaluation and design of Hardware accelerator platforms for speeding up mathematical operations in domains like CFD, Cryptography.
This involves evaluation of commercially available off-th-shelf accelerators like NVIDIA, Clear Speed, and design of FPGA based Accelerator hardware for speeding up Sparse and Dense Matrix multiply operations The group has performed simulation of a sparse matrix X vector multiplication on FPGA . The initial performance estimate for SPMV multiplication for sample matrices is about 12 Gflops per board. The group uses the hardware FPGA board to accelerate the solver performance on large linear systems such as the current reservoir simulation by increasing the single node performance. While the software algorithms group has developed algorithms for handling large matrices on single node, the hardware group is focusing on providing an alternative solution based on FPGA accelerators that are (i) cost effective, (ii) configurable: can be easily adopted for solving different problems and (iii) use low power. Hardware group is also working on Acceleration of Long Integer Operations required for cryptography using FPGA platform.
CRL has research collaborations in a wide set of applications in diversified areas with various academic institutions, scientific organizations and research arms of different firms. CRL continues to enhance product and service capabilities by engaging in proactive research towards futuristic solutions.
